3DIPMC0700

3DIPMC0700

3DIPMC0700

3D Plus

RIMC VHDL IP Core Radiation Hardened DDR2 Solution

3DIPMC0700 is a fully configurable DDR2 SDRAM radiation intelligent memory controller IP core designed to work with 3D PLUS DDR2 memory modules to achieve a radiation hardened DDR2 solution. The 3DIPMC0700 can be configured to support different types of ECC for data width applications from 8b up to 128b; providing SEU mitigation and SEFI protection.

The RIMC IP Core is defined by 2 interfaces: the user interface, which is AMBA compliant, and the DDR PHY interface, compliant to DFI 2.1, to send commands and data to the DDR memory components through the DDR PHY (depends on different FPGAs). The user interface contains at least one AHB bus or AXI bus and one APB bus.

3DIPMC0700 Single Event Upset (SEU) mitigation uses different configurable ECCs (Hamming or ReedSolomon) and scrubbing to correct SEUs and Single Event Row Errors (SERE). For example using a ReedSolomon code for 32b data and 50% overhead [RS(12;8), m=4, Global Bus = 48bits], 3DIPMC0700 can correct up to 8 bits error (row error) in one die per 48b, and 2 SEUs in the same address of different die per 48b. In cases where scrubbing is applied, the worst case (one particle creates 2 upsets in 2 dice) error rate will be 3.8E-9 upset/day/module.

Traditionally, Single Event Functional Interruption (SEFI) mitigation has involved power cycling and/or a device reset after the occurrence of a SEFI; however, power cycling or reset will lead to data loss. To avoid data loss, a specific SEFI protection technique has been designed in the RIMC IP Core to prevent SEFI and to replace this traditional “after SEFI has happened” recovery strategy. This SEFI protection is integrated in the RIMC IP core and is transparent to the user. Verification tests have been performed to confirm the robustness of this protection IP, and no SEFI were observed up to LET > 60Mev-cm²/mg.

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Features
  • High Speed (up to 400MHz) DDR2 memory controller
  • Variable user data width: from x8 to x128b
  • Selectable Hamming or Reed-Solomon coding schemes
  • Configurable number of DDR2 ranks to increase memory capacity
  • Clock & ODT settings compatible with 3D PLUS modules
  • Capability to manage redundant memory designs
  • Selectable Burst of 4 or Burst of 8
  • DDR memory scrubbing can be enabled or disabled
  • Scrubbing can be performed at a user-defined frequency
  • Selectable DRAM refresh time
  • Bank management algorithm instantiated inside the RIMC
  • User interface AMBA® compliant (AXI/AHB/APB)
  • Configurable through AMBA® interfaces
  • Configurable number of AHB/AXI slave interfaces
  • DDR PHY interface DFI 2.1 compliant
  • Dynamically configurable via the 8-bit APB slave interface
  • User can implement anAHBand/orAXI slave interface, 1 to 8 ports can be instantiated
  • Provides a direct access to DDR memory array with a controller bypass mode
Product Type Controller IP Core
Package IP Core
Temperature Range
  • 0°C to +70°C
  • -40°C to +85°C
  • -40°C to +105°C
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Attribute Value
Data Sheet Click here to view

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