RIMC DDR4 SDRAM Controller IP Core
The Radiation Intelligent Memory Controller (RIMC DDR4) is a fully configurable DDR4 SDRAM memory controller IP core designed to operate with 3D PLUS DDR4 memory modules to achieve radiation tolerance improvement. The RIMC contains all standard functions of a DDR memory controller for bus width applications from 8b up to 80b according to PHY limitation. It also includes additional functions, such as Single Event Upset (SEU) mitigation and Single Event Functional Interrupt (SEFI) correction to operate in radiation environments.
In addition to the memory controller IP within the RIMC IP core, the user can either select PHY IPs provided in the IP core or develop his own PHY IP. The RIMC has two primary interfaces, the userinterface (UIF) and the DDR memory interface (DFI).
The UIF features an AHB bus, an AXI bus or UPI, and an APB bus for user dynamic configuration:
- Slave APB interface dedicated to internal registers
- Optional slave AHB/AXI interface
- Optional Bypass interface
- Optional UPI interface (interface compatible with MIG from Xilinx).
Thanks to this interface subsystem, the user is able to use DDR4 SDRAM memories in his design without having to focus on the complex mechanisms required to work in a harsh environment.
|Product Type||Controller IP Core|
|Data Sheet||Click here to view|